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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC33253/D
Advance Information Full Bridge Driver
The MC33253 is a full bridge driver including integrated charge pump, two independent high and low side driver channels. The high and low side drivers include a cross conduction suppression circuit, which, if enabled, prevents the external power FETs from being on at the same time. The drive outputs are capable to source and sink 1 A pulse peak current. The low side channel is referenced to ground, the high side channel is floating above ground. A linear regulator provides a maximum of 15.5V to supply the low side gate driver stages. The high side driver stages are supplied with a 10V charge pump voltage. Such built-in feature, associated to external capacitor provides a full floating high side drive. A under- and over-voltage protection prevents erratic system operation at abnormal supply voltages. Under fault, these functions force the driver stages into off state. The logic inputs are compatible with standard CMOS or LSTTL outputs. The input hysteresis makes the output switching time independent of the input transition time. The global enable logic signal can be used to disable the charge pump and all the bias circuit. The net advantage is the reducuction of the quiescent supply current to under 10A. To wake up the circuit, 5 V has to be provided at G_EN. A built-in single supply operational amplifier could be used to feedback information from the output load to the external MCU. Features:
MC33253
55 VOLT FULL BRIDGE DRIVER
28 1
DW SUFFIX PLASTIC PACKAGE CASE 751F-05 (SO-28)
PIN CONNECTIONS (TOP VIEW) CASE 751F-05 (28 SOIC) 1 2 3 VCC C2 CP_OUT SRC_HS1 ISOUT 28 G_EN 27 /CCS 26 SRC_HS2 25
* * * * * * *
4 5 6 7 8 9 10 11 12 13 14
VCC Operating Voltage Range from 5.5 V up to 55 V VCC2 Operating Voltage Range from 5.5 V up to 28 V Automotive Temperature Range -40C to 125C 1A Pulse Current Output Driver Fast PWM Capability Built-In Charge Pump Cross Conduction Supression Circuit
GATE_HS1 GATE_HS2 24 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A /IN_HS2 23 IN_HS2 22 /IN_LS2 21 IN_LS2 20 GATE_LS2 19 GND2 18 IS-IN 17 IS+IN 16 C1 15
MC33253 ORDERING INFORMATION
Device MC33253DW Temperature Range Package TA = - 40C to +125C Plastic SOIC28
This document contains information on a new product. Specifications and information herein are subject to change without notice.
04/99 (c) Motorola, Inc. 1999
MOTOROLA ANALOG IC DEVICE DATA
REV 1
1
MC33253
SIMPLIFIED BLOCK DIAGRAM
C1 VCC UV/OV Detect VCC G_EN VDD VCC VCC RDY EN GND VCC2 VCC CCS VCC2 EN GND Linear Reg +13.5 V +5.0 V +13.5 V Charge Pump C1 C2 Vpos +13.5 V 5.5 V... 55 V VDD CP_OUT LR_OUT VCC VCC C2 VCC2 VCC2 5.5 V... 28 V
BRG_EN VCC IN_HS1 VCC VCC IN_HS1 VCC IN_LS1 VCC VCC IN_LS1 LOGIC Input & CCS BRG_EN
CCS CCS
HIGH AND LOW SIDE CONTROL WITH CHARGE PUMP
Vgs_ls Vgs_ls VCC
Vgs_hs
VDD/VPOS Level Shift
Pulse Generator G_LOW_HS G_LOW_LS
IN Output Driver
OUT
GATE_HS1 SRC_HS1
VDD/VCC Level Shift
Pulse Generator
IN
Output Driver
OUT
GATE_LS1
HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION VCC IN_HS2 VCC VCC IN_HS2 G_LOW_HS VCC IN_LS2 VCC VCC IN_LS2 HIGH AND LOW SIDE CHANNEL WITH CROSS CONDUCTION SUPPRESSION - SENSE CURRENT AMPLIFIER - + IS+IN IS-IN Input & CCS VDD/VCC Level Shift G_LOW_LS VDD/VPOS Level Shift Pulse Generator BRG_EN CCS Vgs_ls VCC IN Output Driver OUT GATE_HS2 SRC_HS2
Pulse Generator
IN
Output Driver
OUT
GATE_LS2
GND
ISOUT
Figure 1. Principal Building Blocks
2
MOTOROLA ANALOG IC DEVICE DATA
MC33253
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND. Rating Supply Voltage 1 Supply Voltage 2 Linear Regulator Output Voltage High Side Floating Supply Absolute Voltage High Side Floating Supply Offset Voltage High Side Floating Output Voltage Low Side Output Voltage Logic Input Voltage Max VPOSHS Slew Rate Power Dissipation and Thermal Characteristics Maximum Power Dissipation Thermal Resistance Junction-to-Air Operating Junction Temperature Storage Temperature PD RqJA TJ Tstg W C/W C C Symbol VCC VCC2 VLR_out VCP_OUT VSRCHS VGATEHS VGATELS VIN dV/dt Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -- Max 60 28 16 65 65 65 16 10 5.0 Unit VDC VDC VDC VDC VDC VDC VDC VDC V/ns
-40 -65
+150 +150
OPERATING CONDITIONS (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C)
Rating Supply Voltage (VPower) Supply Voltage 2 (VBATT) High Side Floating Supply Absolute Voltage Logic Input Voltage Ambient Temperature Range Symbol VCC VCC2 VCP_OUT VIN TA Min 5.5 5.5 VCC+4 0 -40 Max 55 28 VCC+11 but <65 10 +125 Unit V V V V C
MOTOROLA ANALOG IC DEVICE DATA
3
MC33253
STATIC ELECTRICAL CHARACTERISTICS VCC = 12 V, VCC2 = 12 V, CCP = 33 nF, G_EN = 4.5 V unless otherwise specified. (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C, unless otherwise specified)
Characteristic LOGIC SECTION Logic "1" Input Voltage (IN_LS & IN_HS) Logic "0" Input Voltage (IN_LS & IN_HS) Wake Up Input Voltage (G_EN) Wake Up Current (G_EN) VG_EN = 14 V LINEAR REGULATOR SECTION Linear Regulator VIrout @ VCC2 = 28 V VGS Linear Regulator VIrout @ VCC2 12 V CHARGE PUMP SECTION Charge Pump Output Voltage, ILOAD = 0 mA Charge Pump Output Voltage, ILOAD = 7 mA UNDER/OVERVOLTAGE SECTION Under Voltage Shutdown VCC2 Under Voltage Shutdown VCC Over Voltage Shutdown VCC Over Voltage Shutdown VCC2 OUTPUT SECTION Output Sink Resistor (turned off) VGS = 1.0 V Output Source Resistor (turned on) DVGS = 0, 1V High Side Gate Voltage ON State High Side Gate Voltage OFF State (Reference to SRC_HS) Low Side Gate Voltage ON State Low Side Gate Voltage OFF State SENSE CURRENT AMPLIFIER SECTION (Internal VCC supply @ 7V) Output Dynamic Range (Isink/source = 200A) Open Loop Gain (at 25C) (Note 2) Input Bias Current Input Offset Voltage (at 25C) Input Common Mode Range Sink Capability (Vo > 1.1V) (Note 3) Source Capability (Vo < 5V) (Note 3) Gain Bandwidth Product 28 28 16, 17 16, 17 28 VOH VOL A IIB Vio VICR Isink Isource GBW 4.7 - - - - - 2.0 2.0 - 5.0 - 50 - 2.0 - 3.0 3.0 1.8 - 300 - 1.0 5.0 3.0 - - - V mV dB A mV V mA mA MHz 5, 10 19, 19 24 5, 10 19, 19 24 RDS RDS VGS_HS VGS_HS VGS_LS VGS_LS - - - - - - - - - - - - 5.0 5.0 VCC+11 0.5 15.5 0.5 13 1 1 13 UV2 UV OV OV2 4.6 4.6 56 28 5.1 5.1 64 31 5.5 5.5 70 34 V V V V 3 3 VCP_OUT VCP_OUT VCC + 8 VCC + 8 VCC + 9 VCC + 9 VCC + 11 VCC + 11 V V 12 12 VIrout 13.5 VCC2 - 1 - - 15.5 12 V 27 27 VIH VIL VG_EN IG_EN 2.0 - 4.5 - - - 5.0 V 250 10 0.8 VCC2 500 V V V A Pin # Symbol Min Typ Max Unit
W W
V V V V
NOTE 1 Rise time is given by time needed to charge the gate from 1.0 V to 10 V (vice versa for fall time) NOTE 2 Characterization only NOTE 3 Input Overdrive 1V
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
SUPPLY SECTION Quiescent Supply Current VCC2 (G_EN = 0) Quiescent Supply Current VCC (G_EN = 0) Supply Current VCC Supply Current VCC2 13 1 1 13 IQSD IQSD IOP IOP - - - - - - 0.5 5.0 10 10 3.0 8.0 A A mA mA
DYNAMIC ELECTRICAL CHARACTERISTICS (Typical values for TA = 25C, Min/Max values for TA = -40C to +125C) Prop. Delay HS and LS between 50% input to 50% output, CI = 5.0 nF TPD - 200 300 HS/LS Rise Time @ CI = 5.0 nF, 10% to 90% HS/LS Fall Time @ CI = 5.0 nF, 90% to 10% TRISE TFALL - - 80 80 180 180
ns ns ns
NOTE 1 Rise time is given by time needed to charge the gate from 1.0 V to 10 V (vice versa for fall time) NOTE 2 Characterization only NOTE 3 Input Overdrive 1V
MOTOROLA ANALOG IC DEVICE DATA
5
MC33253
Driver Characteristics Turn-On: For turn-on the current required to charge the gate source capacitor Ciss in the specified time can be calculated as follows: Peak Current for Rise/Fall Time (tr) and a typical PowerMosFET Gate Charge Qg IP = Qg/tr = 75 nC/80 ns 1.0 A
Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Uncontrolled Turn-On of Low Side FET Crss VBAT Flyback Spike pull down HS- Drain VGS Increase Delayed Turn-Off of High Side FET Crss VBAT OFF g_hs L1 g_hs ILOAD Ciss Crss L1 ILOAD Ciss Crss g_hs VGATE -VDRN L1 ILOAD Ciss Crss
Turn-Off: The peak current for turn-off can be obtained in the same way as for turn-on. In addition to the dynamically current, required to turn-off or turn-on the FET, various application related switching scenarios have to be considered:
Flyback Spike charge LS-Gate via Crss Charge Current Irss up to 2.0 A! Delayed Turn-Off of Low Side FET Crss VBAT
Flyback Spike pull down HS- Drain VGS Increase Uncontrolled Turn-On of High Side FET Crss OFF g_hs L1 ILOAD VBAT
Ciss Irss VGATE g_ls OFF Ciss Driver Requirement: Low Resistive Gate-Source Path during OFF-State Crss
g_ls OFF Ciss Driver Requirement: Low Resistive Gate Source Path during OFF-State. High Peak Sink Current Capab.
g_ls
g_ls
Ciss Driver Requirement: High Peak Sink Current Capab.
Ciss Driver Requirement: Low Resistive Gate-Source Path during OFF-State
The output driver sources a peak current of up to 1A for 200 ns to turn on the gate. After 200 ns 100 mA are provided continuously to maintain the gate charged. The output driver sinks a peak current of up to 1A for 200 ns to turn off the gate. After 200 ns 100 mA are sinked continuously to maintain the gate discharged. In order to withstand high dV/dt spikes (up to 10 V/ns) a low resistive path between gate and source is implemented during the off state. Driver Supply The High Side Driver is supplied from the internal charge pump buffered at CP_OUT. The low-drop regulator provides approx. 3.5 mA (fPWM = 50kHz) per gate. In case of the full bridge that means approx. 14 mA, 7.0 mA for the high side and 7.0 mA for the low side. (Note: The average current required to switch a gate with a frequency of 100 kHz is: Average Current (Charge Pump) for PWM Frq. (fPWM) ICP = Qg*fPWM = 75 nC*100 kHz = 7,5 mA
A full bridge application switch only one high side and one low side at the same time.) External capacitors on Charge Pump and on Linear Regulator are necessary to supply high peak current absorbed during switching. The Low Side Driver is supplied from built in low drop regulator. Gate Protection The low side gate is protected by the internal linear regulator, which guarantees that VGATE_LS does not exceed the maximum VGS. Especially when working with the charge pump the voltage at POS_HS can be up to 65 V!. The high side gate is clamped internally, in order to avoid a VGS exceeding 14 V. The Gate protection does not include a Flyback Voltage Clamp that protects the driver and the external FET from a Flyback voltage that can appear when driving inductive load. This Flyback voltage can reach high negative voltage values and needs to be clamped externally.
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
Vgs_ls Vgs_hs M1 IN Output Driver G_LOW OUT GATE_HS VGS < 14 V under all conditions L1 M2 IN Output Driver OUT GATE_LS Inductive Flyback Voltage Clamp VCC
SRC_HS Dcl
G_LOW
Figure 2. Gate Protection and Flyback Voltage Clamp
TMOS Failure Protection All output driver stages are protected against TMOS failure conditions. If one of the external power FETs is destroyed (Gate = VCC, or Gate = Gnd) the function of the remaining output driver stages is not affected. All output drivers are short circuit protected against short circuits to ground.
Cross Conduction Suppression The purpose of the cross conduction suppression is to avoid that high and low side FET are turned on at the same time, which prevents the half bridge power FETs of a shoot- through condition. The CCS can be disabled / enabled by an external signal (/CCS).
MOTOROLA ANALOG IC DEVICE DATA
7
MC33253
VCC G_EN AND AND EN_CP/LDO UV_OV VCC CCS VDD VCC IN_HS 10 k AND 10 k IN_HS VDD 10 k AND VCC AND OR en1_ls VCC IN_LS AND drv_ls en2_ls AND G_LOW_LS "1" FET is Turned-Off OUT_LS "1" Turn-On FET VCC en1_hs OR en2_hs drv_hs AND OUT_HS "1" Turn-On FET G_LOW_HS "1" FET is Turned-Off BRG_EN CCS ChP_RDY "0" Cross Conduction Suppression is Enabled en2hs = G_LOW_LS, en2ls = G_LOW_HS en1hs = drv_ls, en1ls = drv_hs "1" Cross Conduction Suppression is Disabled en2hs = "1", en2ls = "1" en1hs = "0", en1ls = "0" "1" Enable Charge Pump and LDO "1" Supply is ok "0" Under Voltage or Over Voltage Condition "1" Charge Pump is Ready
IN_LS
Figure 3. Input Logic and Cross Conduction Suppression
Logic Inputs Logic Input Voltage Range: (Max. Operating) -0.3 V ... 10 V Wake Up Function: (G_EN) 4.5 V ... VCC2 During Wake-Up the logic is supplied from the G_EN pin. Low Drop Linear Regulator The low drop linear regulator provides the 5.0 V for the logic section of the driver, the Vgs_ls buffered at LR_OUT and the +13.5 V for the charge pump, which generates the Vgs_hs. The low drop linear regulator provides 3.5 mA average current per driver stage. If VCC2 exceeds 14 V the output is limited to 14.5 V. Charge Pump The charge pump generates the high side driver supply voltage (Vgs_hs), buffered at CP_OUT. Vgs_hs = VCC + VCC2 - 1.2 V. The average output current is ICP = 3.5 mA (fPWM = 50 kHz) per output driver. The charge pump charges an external storage capacitor, which provides the peak switching current to the high side output drivers.
Sense Current OP-Amp Typically shunt resistivity is dimensioned as low as possible (50 mOhm/10 A). The typical voltage generated by sensing the current is in the range of 500 mV. The A/D input of typical micro controller is in the range of 5.0 V. That requires a voltage gain of 10.
Over / Under Voltage Shutdown The under voltage protection becomes active at VCC below 5.5 V and the overvoltage protection is activated at VCC above 55 V or at VCC2 above 28 V. If the OUV protection is activated the outputs are driven low, in order to switch off the FETs.
Protection A protection against double battery and load dump spikes up to 55 V is given by VCC = 55 V. A protection against reverse polarity is given by the external power FET with the free wheeling diodes, forming a conducting pass from ground to VCC. An additional protection is not provided within the circuit. There is a temperature shut down protector per each half bridge. It protects the circuitry against temperature damage by blocking the output drives.
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
APPLICATION DIAGRAM
Both applications utilize the internal charge pump to provide the high side floating voltage. This voltage can be provided by an external source also.
VBAT VLOGIC VCC/VCC2 /G_EN /CCS C1 C2 IN_HS1 IN_LS1 IN_HS2 IN_LS2 ISOUT R1 LR_OUT CP_OUT
C1
C3
M1
M3
C2 CAN PWM1 PWM2 PWM3 PWM4 HS_1 LS_1 HS_2 LS_2 CURRENT FDBK
GATE_HS1 SRC_HS1 FULL BRIDGE DRIVER GATE_LS1 GATE_HS2 SRC_HS2 GATE_LS2 IS-IN IS+IN GND G G Lm
M2
M4
mC
SS R2 Rsh
SL
SS
SL
Figure 4. DC Motor Control with Micro Controller
VBAT ON/OFF VCC/VCC2 /G_EN /CCS C1 C2 IN_HS1 LEFT/RIGHT IN_LS1 IN_HS2 IN_LS2 LR_OUT CP_OUT
C1
C3
M1
M3
C2
GATE_HS1 SRC_HS1 FULL BRIDGE DRIVER GATE_LS1 GATE_HS2 SRC_HS2 GATE_LS2 IS-IN IS+IN GND Lm
M2
M4
Figure 5. DC Motor Control (low cost)
MOTOROLA ANALOG IC DEVICE DATA
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MC33253
PIN DEFINITIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VCC C2 CP_OUT SRC_HS1 GATE_HS1 /IN_HS1 IN_HS1 /IN_LS1 IN_LS1 GATE_LS1 GND1 LR_OUT VCC2 GND_A C1 IS+ IS- GND2 GATE_LS2 IN_LS2 /IN_LS2 IN_HS2 /IN_HS2 GATE_HS2 SRC_HS2 /CCS G_EN IS_OUT Supply 1 Charge Pump Capacitor Charge Pump Out Source 1 Output High Side Gate 1 Output High Side Neg. Input High Side 1 Pos. Input High Side 1 Neg. Input Low Side 1 Pos. Input Low Side 1 Gate 1 Output Low Side Ground Linear Regulator Output Supply 2 Analog Ground Charge Pump Capacitor Sense OpAmp Pos. Input Sense OpAmp Neg. Input Ground 2 Gate 2 Output Low Side Pos. Input Low Side 2 Neg. Input Low Side 2 Pos. Input High Side 2 Neg. Input High Side 2 Gate 2 Output High Side Source 2 Output High Side Enable Cross Conduction Supression Global Enable Sense Current OpAmp Output Pin Description
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MOTOROLA ANALOG IC DEVICE DATA
MC33253
PACKAGE DIMENSIONS
A
D
28 15 M
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 4. MAXIMUM MOLD PROTRUSION 0.015 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 2.35 2.65 0.13 0.29 0.35 0.49 0.23 0.32 17.80 18.05 7.40 7.60 1.27 BSC 10.05 10.55 0.41 0.90 0_ 8_
E
H
1 14 PIN 1 IDENT
B
0.25
M
B
L 0.10
SEATING PLANE
e B 0.025
M
C
DIM A A1 B C D E e H L
A1
A
C CA
S
B
q
q
S
CASE 751F-05 ISSUE F
MOTOROLA ANALOG IC DEVICE DATA
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MC33253
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MC33253/D MOTOROLA ANALOG IC DEVICE DATA

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